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whulaisla
whulaisla
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whulaisla
http://www.docin.com/whulaisla

他还没有介绍自己~

私信
whulaisla
  • 文档 14
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  • 总浏览量 253
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最近上架的文档

designing bang-bang PLLs for clock and data recovery in serial data transmission systems 12 p
designing bang-bang PLLs for clock and data recovery in serial data transmission systems
Thesis-important-verilog A design of DPLL 69 p
Thesis-important-verilog A design of DPLL
Sub Sampling PLL techniques 8 p
Sub Sampling PLL techniques
Understanding jitter and wander measurements and standards 140 p
Understanding jitter and wander measurements and standards
A Clock and Data Recovery Circuit With Programmable Multi-Level Phase Detector Characteristics and a Built-in Jitter Monitor 9 p
A Clock and Data Recovery Circuit With Programmable Multi-Level Phase Detector Characteristics and a Built-in Jitter Monitor
A 40-Gbs CDR Circuit With Adaptive Decision-Point Control Based on Eye-Opening Monitor Feedback 10 p
A 40-Gbs CDR Circuit With Adaptive Decision-Point Control Based on Eye-Opening Monitor Feedback
A 25-Gbps 5-mW CDR Deserializer in 65-nm Technology 95 p
A 25-Gbps 5-mW CDR Deserializer in 65-nm Technology
Three-Stage Dynamic-Biased CMOS Amplifier With a Robust Optimization of the Settling Time 11 p
Three-Stage Dynamic-Biased CMOS Amplifier With a Robust Optimization of the Settling Time
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