SystemVerilog_3.1_final
本文档由 eecsseudl 分享于2010-01-18 13:13
This SystemVerilog Language Reference Manual was developed by experts from many different fields, includingdesign and verification engineers, Electronic Design Automation (EDA) companies, EDA vendors, andmembers of the IEEE 1364 Verilog standard working group.The SystemVerilog Language Reference Manual (LRM) was specified by the Accellera SystemVerilog committ..
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君,已阅读到文档的结尾了呢~~